The figure shows 2 NAND gates followed by a N | vedclass

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(D) The circuit consists of two $NAND$ gates whose outputs are fed into a $NOR$ gate. Let the inputs be $X, Y, Z$. The output of the first $NAND$ gate

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$AND$

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(D) The circuit consists of two $NAND$ gates whose outputs are fed into a $NOR$ gate. Let the inputs be $X, Y, Z$. The output of the first $NAND$ gate is $A = \overline{X \cdot Y}$ and the output of the second $NAND$ gate is $B = \overline{Y \cdot Z}$. These are the inputs to the $NOR$ gate,so the final output is $R = \overline{A + B} = \overline{\overline{X \cdot Y} + \overline{Y \cdot Z}}$. Using De Morgan's theorem,$R = \overline{\overline{X \cdot Y}} \cdot \overline{\overline{Y \cdot Z}} = (X \cdot Y) \cdot (Y \cdot Z) = X \cdot Y \cdot Z$. This is the Boolean expression for an $AND$ gate with three inputs. Thus,the system is equivalent to an $AND$ gate.

Input $A$	Input $B$	Output $Y$
$0$	$1$	$C$
$0$	$0$	$D$
$1$	$0$	$E$
$1$	$1$	$F$

The figure shows $2$ $NAND$ gates followed by a $NOR$ gate. The system is equivalent to one gate $G$ with inputs $X, Y, Z$ and output $R$. What is $G$?

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What is the output $Y$ in the following circuit, when all the three inputs $A, B, C$ are first '$0$' and then '$1$'?

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