If {V}_{A} and {V}_{B} are the input voltages | vedclass

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(B) For circuit $(A)$:${V}_{A} = 5\, V \Rightarrow A = 1$,${V}_{A} = 0\, V \Rightarrow A = 0$${V}_{B} = 5\, V \Rightarrow B = 1$,${V}_{B} = 0\, V \Rig

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$OR$ and $NOT$ Gate

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(B) For circuit $(A)$:${V}_{A} = 5\, V \Rightarrow A = 1$,${V}_{A} = 0\, V \Rightarrow A = 0$${V}_{B} = 5\, V \Rightarrow B = 1$,${V}_{B} = 0\, V \Rightarrow B = 0$If $A = B = 0$,both diodes are reverse biased,so ${V}_{0} = 0\, V$.If $A = 1, B = 0$,diode ${D}_{1}$ is forward biased,so ${V}_{0} = 5\, V$.If $A = 0, B = 1$,diode ${D}_{2}$ is forward biased,so ${V}_{0} = 5\, V$.If $A = 1, B = 1$,both diodes are forward biased,so ${V}_{0} = 5\, V$.This truth table corresponds to an $OR$ gate.For circuit $(B)$:This is a common-emitter $npn$ transistor configuration.When input voltage is $0\, V$ $(A = 0)$,the base-emitter junction is not forward biased,the transistor is in cut-off,and ${V}_{0} = 5\, V$ (logic $1$).When input voltage is $5\, V$ $(A = 1)$,the base-emitter junction is forward biased,the transistor goes into saturation,and ${V}_{0} \approx 0\, V$ (logic $0$).This inversion behavior corresponds to a $NOT$ gate.Therefore,the gates are $OR$ and $NOT$.

If ${V}_{A}$ and ${V}_{B}$ are the input voltages (either $5\, V$ or $0\, V$) and ${V}_{0}$ is the output voltage,then the two gates represented in the following circuit $(A)$ and $(B)$ are:

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