Three logic gates are connected as shown in t | vedclass

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(A) The circuit consists of a $NAND$ gate, a $NOR$ gate, and an $AND$ gate.$1$. The $NAND$ gate has inputs $A=1$ and $B=0$. The output $y_1$ of a $NAN

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$1, 0, 0$

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(A) The circuit consists of a $NAND$ gate, a $NOR$ gate, and an $AND$ gate.$1$. The $NAND$ gate has inputs $A=1$ and $B=0$. The output $y_1$ of a $NAND$ gate is given by $y_1 = \overline{A \cdot B}$. Thus, $y_1 = \overline{1 \cdot 0} = \overline{0} = 1$.$2$. The $NOR$ gate has inputs $B=0$ and $C=1$. The output $y_2$ of a $NOR$ gate is given by $y_2 = \overline{B + C}$. Thus, $y_2 = \overline{0 + 1} = \overline{1} = 0$.$3$. The $AND$ gate has inputs $y_1=1$ and $y_2=0$. The output $y_3$ of an $AND$ gate is given by $y_3 = y_1 \cdot y_2$. Thus, $y_3 = 1 \cdot 0 = 0$.Therefore, the values are $y_1=1, y_2=0, y_3=0$.

Three logic gates are connected as shown in the figure. If the inputs are $A=1, B=0$ and $C=1$, then the values of $y_1, y_2$ and $y_3$ respectively are

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