In the following combinations of logic gates, | vedclass

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(A) For circuit $A$: The inputs to the $NAND$ gate are $1$ and $1$,so its output is $0$. This $0$ passes through a $NOT$ gate,becoming $1$. The $OR$ g

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$1, 1, 0$

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(A) For circuit $A$: The inputs to the $NAND$ gate are $1$ and $1$,so its output is $0$. This $0$ passes through a $NOT$ gate,becoming $1$. The $OR$ gate receives inputs $1$ and $0$,resulting in an output of $1$.For circuit $B$: The inputs $0$ and $1$ pass through $NOT$ gates,becoming $1$ and $0$ respectively. These are inputs to a $NAND$ gate. Since $1 	ext{ AND } 0 = 0$,the $NAND$ gate (which is $NOT$-$AND$) outputs $1$.For circuit $C$: The $OR$ gate receives inputs $1$ and $1$,resulting in an output of $1$. However,the diagram shows the $OR$ gate is followed by a $NOT$ bubble (making it a $NOR$ gate),so the output is $0$. This $0$ and the input $1$ are fed into an $AND$ gate,resulting in an output of $0$.Thus,the outputs are $1, 1, 0$ respectively.

In the following combinations of logic gates,the outputs of $A, B$ and $C$ are respectively

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