The combination of NAND gates is shown in the | vedclass

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(C) The two $NAND$ gates whose inputs are joined together act as $NOT$ gates. Let the inputs be $A$ and $B$. The outputs of the first two $NAND$ gates

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$OR$ gate

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(C) The two $NAND$ gates whose inputs are joined together act as $NOT$ gates. Let the inputs be $A$ and $B$. The outputs of the first two $NAND$ gates are $y_1 = \overline{A}$ and $y_2 = \overline{B}$. These are fed into the third $NAND$ gate. The final output is $y = \overline{y_1 \cdot y_2} = \overline{\overline{A} \cdot \overline{B}}$. By De Morgan's theorem, $y = \overline{\overline{A}} + \overline{\overline{B}} = A + B$. This is the Boolean expression for an $OR$ gate. The truth table is as follows:| $A$ | $B$ | $y_1$ | $y_2$ | $y$ ||---|---|---|---|---|| $0$ | $0$ | $1$ | $1$ | $0$ || $0$ | $1$ | $1$ | $0$ | $1$ || $1$ | $0$ | $0$ | $1$ | $1$ || $1$ | $1$ | $0$ | $0$ | $1$ |Thus, the combination is equivalent to an $OR$ gate.

The combination of $NAND$ gates is shown in the figure. It is equivalent to which gate?

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