When the two inputs of a NAND gate are shorte | vedclass

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(C) $NAND$ gate is defined as an $AND$ gate followed by a $NOT$ gate. The Boolean expression for a $NAND$ gate with inputs $A$ and $B$ is $Y = \overli

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$NOT$

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(C) $NAND$ gate is defined as an $AND$ gate followed by a $NOT$ gate. The Boolean expression for a $NAND$ gate with inputs $A$ and $B$ is $Y = \overline{A \cdot B}$.When the two inputs are shorted,$A = B$. Substituting this into the expression,we get $Y = \overline{A \cdot A} = \overline{A}$.This is the Boolean expression for a $NOT$ gate.The truth table for this configuration is:$A$$Y = \overline{A \cdot A}$$0$$1$$1$$0$Since the output is the inverse of the input,the resulting gate is a $NOT$ gate.

When the two inputs of a $NAND$ gate are shorted,the resulting gate is

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